Shallow trench isolation and the scaling of isolation with transistor size is an issue for conventional transistor manufacturing. Shallow trench isolation (STI) is an integrated circuit feature which prevents electric current leakage between adjacent semiconductor device components. STI is generally used on CMOS process technology nodes of 250 nanometers and smaller. STI is created early during the semiconductor device fabrication process, before transistors are formed. The key steps of the STI process involve etching a pattern of trenches in the silicon, depositing one or more dielectric materials (such as silicon dioxide) to fill the trenches, and removing the excess dielectric using a technique such as chemical-mechanical planarization.
In conventional manufacturing of transistors such as finFETs, a spin on dielectric (SOD) or flowable oxide is used to fill the gaps between fins of a finFET due to the filling capability into the high aspect ratio trench. Spin-on organic polymeric dielectrics are generally polymeric dielectrics that are deposited by a spin-on approach, such as those traditionally used to deposit photoresist, rather than chemical vapor deposition. Integration difficulties include low mechanical strength and thermal stability. Some examples of spin-on organic polymers are polyimide, polynorbornenes, benzocyclobutene, and PTFE. However, this SOD material is not very dense. For example, during curing the degasing of the SOD material leave holes or voids inside the STI oxide. Those holes or weak spots lead to finFET yield issues by causing gate to source/drain shorts.
Accordingly, there is a need for systems, apparatus, and methods that overcome the deficiencies of conventional approaches including the methods, system and apparatus provided hereby.